工作類別: 數位ic設計工程師

選自Cake與104人力銀行網站,履歷投遞後由各招聘公司直接查看與安排後續面試流程。

資源 Source: 104
緯創軟體股份有限公司

T-Engineer for IC design(遠端)

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: …
待遇面議
[台北市南港區 Nangang District, Taipei City]
資源 Source: 104
Qualcomm Semiconductor Corporation_高通半導體有限公司

SRAM Characterization and Modeling Engineer (3078557)

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表: https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/SRAM-Characterization-and-Modeling-Engineer_3078557 【Talents who apply job …
待遇面議
[新竹縣竹北市 Zhubei City, Hsinchu County]
資源 Source: 104
Qualcomm Semiconductor Corporation_高通半導體有限公司

IP Memory Design Engineer (Hsinchu) (3059285)

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: …
待遇面議
[新竹市 Hsinchu City]
資源 Source: 104
緯創軟體股份有限公司

T-MTS Silicon Design Engineer(遠端)

Responsible for industry leading IP Synthesis/Formal/STA. 2 .Responsible for industry leading IP LINT/CDC/VSI. Responsible for industry leading IP regularly regression. …
待遇面議
[台北市南港區 Nangang District, Taipei City]
資源 Source: 104
智原科技股份有限公司

PLL/DLL Design Engineer

General OSC/PLL/DLL/SSCG/CDR design & production experience LC-tank VCO design & production experience CDR design & production experience
待遇面議
[新竹市 Hsinchu City]
資源 Source: 104
智原科技股份有限公司

DDR-PHY Digital Designer

DRAM DDRPHY Digital Part Circuit Design: 1. study and know the spec of DRAM (inculdeDDR5/DDR4/DDR4/LPDDR5/LPDDR4/LPDDR3) 2. study and know the protocol between memory controller 3. …
待遇面議
[新竹市 Hsinchu City]
資源 Source: 104
安霸股份有限公司

VLSI Physical Design Manager/Designer (KW: APR, P&R)

The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in …
待遇面議
[新竹市 Hsinchu City]
資源 Source: 104
安霸股份有限公司

Physical Design Methodology/CAD Manager (KW: APR, P&R)

1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …
待遇面議
[新竹市 Hsinchu City]