G240009-DFT Technical Manager/Sr. Engineer

※ Job Contents:

• Block/Chip level DFT feature and architecture definition.
• DFT specification generation and review with customer co-work.
• Implement block/chip level DC/AC SCAN, BSD, MBIST, Memory Repair, System BIST and IP macro test.
• Deliver quality DFT timing constraints and support BE team timing closure.
• Do all verifications on DFT structures, and deliver quality production ATE patterns.
• Support ATE bring-up, and debug the ATE patterns for production flow, DFT diagnosis for yield improvement.
• Lead DFT implementation team to support projects and review with customers and outsourcing vendor
• DFT resource and schedule planning
• DFT negotiation with Pre-Sales Customer

※ Requirements:

• More than 5 years project experience in DFT design implementation.
• Hand-on experience in Synopsys (DFT Compiler/TetraMax/VCS) and Mentor (Tessent MBIST/Scan).
• English communication skill.
• DFT Lead Capability: DFT Planning, resource/schedule planning, communicating with customers and outsourcing vendor