G230018-Physical Design Staff/Technical Manager

Physical Design Staff ※ Job Contents:

  1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing.
  2. Support STA timing analysis and fixing
  3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements:
  4. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler.
  5. TOEIC 730~855 is preferred.
  6. 3 years+ exp, have experiences in 16/12/7/5nm IC design experiences will be plus.

Physical Design Manager/Technical Manager

  1. Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing
  2. Support STA timing analysis and fixing
  3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis
  4. Be the block coordinator for a hierarchical design
  5. Take responsibility for schedule control and awareness about critical issues
  6. Training and coaching flash/junior engineers
  7. 7 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus