G230018-Physical Design Staff/Technical Manager
Physical Design Staff ※ Job Contents:
- Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing.
- Support STA timing analysis and fixing
- Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements:
- Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler.
- TOEIC 730~855 is preferred.
- 3 years+ exp, have experiences in 16/12/7/5nm IC design experiences will be plus.
Physical Design Manager/Technical Manager
- Perform TOP or big-scale sub Top Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing
- Support STA timing analysis and fixing
- Perform physical verification, including DRC, LVS, IR drop and DFM analysis
- Be the block coordinator for a hierarchical design
- Take responsibility for schedule control and awareness about critical issues
- Training and coaching flash/junior engineers
- 7 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus