S－ ASIC/SOC RTL Design Engineer｜全球知名CPU、GPU大廠（台北/新竹）

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

【Key Responsibilities】

• Responsible for front-end digital logic design in ASIC/SOC projects.
• Perform HDL coding (Verilog/SystemVerilog).
• Prepare and maintain design documentation (specifications and design documents).
• Conduct RTL quality checks (Lint, CDC, power analysis, etc.).
• Collaborate with Backend/Physical Design engineers to achieve timing closure.

【Core Requirements】

• Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience.
• RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL.
• TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA.
• EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis).
• Documentation: Ability to write design specifications and technical documents.
• Collaboration: Work closely with the Design Verification (DV) team on IP verification.

【Preferred Qualifications】

• Familiarity with CPU architectures (x86/ARM/8051).
• Knowledge of AMBA bus protocols (AXI/AHB/APB).
• Understanding of PCIe protocol.digital IP/SOC design verification.