【國際大型IC, 半導體公司】Timing Signoff Manager_207HC

Responsibilities : 1.Responsible on STA / design constraint validation for advanced technology nodes. 2.Develop new Timing Signoff flow. 3.Co-work with PD owners for Project Timing Closure.

Requirements : 1.Ph.D or Master degree in EE or CS. 2.10+ years of experience in STA / Front-end domain. 3.Experience on tape-out advanced-node chips, i.e., 7nm and below. 4.Strong knowledge in IC design flow, microelectronics theory. 5.Expert-level signoff skill on Synopsys Primetime or Cadence Tempus 6.Strong technical capability in problem solving and researching.