DRAM Circuit Designer, up to Sr. Staff (3081820)

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508109

【Job Overview】

The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential.

【Responsibilities】

• Design and optimize memory core circuits for higher sense margin, improved array timing, area • Develop and optimize DRAM circuits and timing control for performant, area, and energy efficient cell array • Develop bank array placement strategies across various bank array, TSV, and power distribution choices • Develop novel fabrics for best/robust distribution of high-bandwidth busses across the DRAM array, compute, and IO • Create layouts that optimize circuit placement, signal routing, and power delivery • Develop robust power delivery to the array design • Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness • Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads • Floorplan DRAM circuits under manufacturing constraints, testability, repairability, and high performance