DRAM Bus and PDN Designer, up to Sr. Staff (3081816)

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508110

【Job Overview】

The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design bus circuits and power distribution network for the custom DRAM to improve system KPIs such as bandwidth, latency, power, and thermal. The candidate will work on solutions of high-speed and high-bandwidth bus design for advanced memory. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential.

【Responsibilities】 -Develop and optimize circuits for high-bandwidth memory bus and PDN control, timing, and control -Analyze and ensure the integrity of signals on the bus and PDN across PVT corners -Develop and validate the bus behavior for various access protocols to meet throughput, latency, and energy specifications -Develop novel fabrics for best/robust distribution of high-bandwidth busses and PDN across the DRAM array, compute, and IO -Create layouts that optimize the bus and PDN placement for routability across the whole chip -Use state-of-the-art design and simulation tools to simulate the bus behavior and manufacture readiness -Develop behavioral, timing, and power models of the bus to guide the architecture choices across AI, compute, and mobile workloads -Develop power modeling framework to build state-dependent power and determine PMIC requirements -Floorplan 3D DRAM chips under 3D integration manufacturing constraints, testability, repairability, and high performance