3D DRAM Architecture, up to Sr. Staff (3081821)

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 Apply here: https://careers.qualcomm.com/careers/job/446715508019

【Job Overview】

The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits. The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential.

【Responsibilities】

• Develop and optimize 3D DRAM bank organization and near-memory computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W •Develop and validate models for 3D DRAM performance, power, and yield as function of bank, TSV, and power distribution choices •Develop novel fabrics for best/robust distribution of high-bandwidth data from 3D DRAM memory arrays to the near-memory computing units across various workloads for mobile, compute, and XR applications •Develop power distribution topology that enable robust DRAM operation in the 3D stack •Simulate and emulate system performance of 3D DRAM architecture choices across AI, compute, and mobile workloads •Floorplan 3D DRAM chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability, and high performance