Job category: 數位ic設計工程師

1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …

Physical Design Staff ※ Job Contents: Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. Support STA …

Develop advanced memory compilers, evaluate new memory architectures and methodologies Perform memory design QA flow and propose continuous improvement plans Provide technical …

Job Contents: Communicate with customers to provide suitable test architecture planning for project scope Working with the APR team to ensure to correct DFT implementation …

General OSC/PLL/DLL/SSCG/CDR design & production experience LC-tank VCO design & production experience CDR design & production experience

Pantherun is a cyber security and data communications company that has designed a One-of-a-kind Chip and software based Intellectual Property for secure Ethernet Communication …

Job Description: The selected candidate will have to handle RTL design implementation, simulation verification, FPGA verification, Chip integration (floorplan design, package …

Chip Application Front-End Staff ※ Job Contents: Took responsibility of creating SDC for the complex SoC. Took responsibility of timing analysis with customer. Took responsibility …