Job category: 類比ic設計工程師

Perform synthesis, DFT, floorplan, power planning, placement, CTS, routing, timing closure, ECO, IR/EM signoff, and physical verification. Manage schedule, resolve design and flow …

Define, manage, and execute design verification strategies for complex semiconductor projects. Work directly with Taiwanese clients to ensure successful project delivery and …

Define, manage, and execute design verification strategies for complex semiconductor projects. Work directly with Taiwanese clients to ensure successful project delivery and …

Propose design verification plan and do the execution based on IP and system HW architecture/application Develop design verification environment Develop required verification …

Work in PD flow: synthesis, DFT, floorplan, power planning, placement, CTS, routing, timing closure, ECO, IR/EM signoff, and physical verification is a plus. Co-work with physical …

Ability to investigate spec, update testlist, build test case; knowledge of SVA, coverage analysis is plus. Co-work with design verification teams.

Responsible for industry leading IP Synthesis/Formal/STA. 2 .Responsible for industry leading IP LINT/CDC/VSI. Responsible for industry leading IP regularly regression. …

General Solution Architect / Execution PM ※Job Contents Handle project execution & management for advanced ASIC chip from Netlist-in to GDSII tapeout and silicon bring-up at …