1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …
類比電路開發設計與佈局優化(Bandgap, LDO, Charge Pump等類比電路) 非揮發性記憶體電路開發設計(Array, Decoding, Sense Amplifier等電路) 消費性、物聯網與車用電子之非揮發性記憶體電路整合開發設計 Our Design Team is responsible for NVM …
Job responsibilities:
Design testing and verification plans of our RF SoC products: bring-up of test chip and production chips, function verification, performance verification, …
Job responsibilities:
Based on product requirements, support RD to create test plan, and suggest testing platform Test program development and debugging Test hardware (Probe card, …
Responsible for Ethernet communication device designs such as Ethernet switch, IoT, RTU, etc by using FPGA main chip. Main scope also include FPGA (such as Xilinx and Intel …
Responsible for Ethernet communication device designs such as Ethernet switch, IoT, RTU, etc by using FPGA main chip. Main scope also include FPGA (such as Xilinx and Intel …
As a Regulatory Compliance Engineer, you will play a crucial role in ensuring our products meet the highest standards of EMC, Safety, and Radio compliance for global certification …
The lead engineer is responsible for the preparation of the technical part of a project specific proposal. These include the responsibility for a timely response to the commercial …